1. Field of the Invention
This invention relates to microprocessors, and more particularly, to embedding variable length instructions within a long instruction word.
2. Description of the Relevant Art
Early microprocessors used instruction sets having variable length instructions. Varying the instruction length allowed for efficient utilization of storage space and memory which were scarce resources at the time. An example of a variable length instruction set is the x86 instruction set. A generic format illustrative of the x86 instruction set is shown in FIG. 1. As illustrated in the figure, an x86 instruction consists of from one to five optional prefix bytes 102, followed by an operation code (opcode) field 104, an optional addressing mode (Mod R/M) byte 106, an optional scale-index-base (SIB) byte 108, an optional displacement field 110, and an optional immediate data field 112.
Opcode field 104 defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more prefix bytes. For example, a prefix byte may be used to change the address or operand size for an instruction, to override the default segment used in memory addressing, or to instruct the processor to repeat a string operation a number of times. Opcode field 104 follows prefix bytes 102, if any, and may be one or two bytes in length. Addressing mode (Mod R/M) byte 106 specifies the registers used as well as memory addressing modes. Scale-index-base (SIB) byte 108 is used only in 32-bit base-relative addressing using scale and index factors. A base field of the SIB byte specifies which register contains the base value for the address calculation, and an index field specifies which register contains the index value. A scale field specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is optional displacement field 110, which may be from one to four bytes in length. Displacement field 110 contains a constant used in address calculations. Immediate field 112 is optional and may also be from one to four bytes in length. It contains a constant used as an instruction operand. The shortest x86 instructions are only one byte long, and comprise a single opcode byte. The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386 and 80486 both allow instruction lengths of up to 15 bytes.
In the mid-1980's as memory and storage became less expensive, reduced instruction set computers (RISC) debuted using fixed instruction lengths. Fixed instruction lengths advantageously reduced the microprocessor resources required to fetch, align and decode an instruction. Consequently, RISC instruction sets allowed for greater performance.
Since the introduction of the RISC architecture, further improved architectures have been proposed. One proposed architecture bundles multiple RISC instructions into groups called long instruction words (LIW). FIG. 2 illustrates one proposed LIW format. LIW 120 comprises one dependency field 122 and three instruction fields 124, 126, and 128. Dependency field 122 identifies which instructions within instruction word 120, if any, are dependent upon other instructions. Each instruction field 124, 126, and 128 is of equal length (in this case 40 bits) and is designed to hold one individual RISC instruction comprising an opcode and number of fields defining register operands. Other proposed architectures eliminate dependency field 122 in favor of a LIW without any dependencies between the instructions whatsoever.
LIW architectures offer many of the advantages of RISC architectures while improving the ability of the microprocessor to execute instructions in parallel. However, the widespread acceptance of the x86 family of microprocessors by consumers and software developers has led microprocessor designers to forego the benefits of RISC and LIW architectures in favor of compatibility with the large amount of software available for the x86 instruction set.
Continuing improvements in process technologies have further magnified the potential advantages of the LIW architecture. As process technologies allow microprocessors to have greater numbers of transistors, the ability to put these transistors to work in parallel becomes more important. LIW architectures provides a parallel structure capable of taking advantage of the large numbers of transistors likely to be in future microprocessors. As a result, microprocessor designers are faced with an increasingly difficult decision of whether to forgo backward compatibility with x86 instructions in pursuit of higher performance.
One proposed solution is to design a RISC or LIW microprocessor and provide backward compatibility by using software or microcode to translate all x86 instructions into RISC or LIW format. Unfortunately, this solution typically yields unsatisfactory performance for x86 software because the translation process greatly slows execution and generates a large amounts of non-optimized code. Therefore, a solution providing both the advantages of a LIW architecture with reasonable performance for variable length instructions is needed.